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irfz24ns/l hexfet ? power mosfet pd - 9.1355b l advanced process technology l surface mount (irfz24ns) l low-profile through-hole (irfz24nl) l 175c operating temperature l fast switching l fully avalanche rated parameter typ. max. units r jc junction-to-case CCC 3.3 r ja junction-to-ambient ( pcb mounted,steady-state)** CCC 40 thermal resistance c/w parameter max. units i d @ t c = 25c continuous drain current, v gs @ 10v ? 17 i d @ t c = 100c continuous drain current, v gs @ 10v ? 12 a i dm pulsed drain current ?? 68 p d @t a = 25c power dissipation 3.8 w p d @t c = 25c power dissipation 45 w linear derating factor 0.30 w/c v gs gate-to-source voltage 20 v e as single pulse avalanche energy ?? 71 mj i ar avalanche current ? 10 a e ar repetitive avalanche energy ? 4.5 mj dv/dt peak diode recovery dv/dt ?? 6.8 v/ns t j operating junction and -55 to + 175 t stg storage temperature range soldering temperature, for 10 seconds 300 (1.6mm from case ) c absolute maximum ratings fifth generation hexfets from international rectifierutilize advanced processing techniques to achieve extremely low on-resistance per silicon area. this benefit, combined with the fast switching speed and ruggedized device design that hexfet power mosfets are well known for, provides the designer with an extremely efficient and reliable device for use in a wide variety of applications. the d 2 pak is a surface mount power package capable of accommodating die sizes up to hex-4. it provides thehighest power capability and the lowest possible on- resistance in any existing surface mount package. the d 2 pak is suitable for high current applications because of its low internal connection resistance and can dissipateup to 2.0w in a typical surface mount application. the through-hole version (irfz24nl) is available for low- profile applications. description v dss = 55v r ds(on) = 0.07 i d = 17a 2 d pak to-262 s d g 9/22/97 downloaded from: http:///
irfz24ns/l ? starting t j = 25c, l =1.0mh r g = 25 , i as = 10a. (see figure 12) ? repetitive rating; pulse width limited by max. junction temperature. ( see fig. 11 ) notes: ** when mounted on 1" square pcb (fr-4 or g-10 material ). for recommended footprint and soldering techniques refer to application note #an-994. ? i sd 10a, di/dt 280a/s, v dd v (br)dss , t j 175c ? pulse width 280s; duty cycle 2%. ? uses irfz24n data and test conditions parameter min. typ. max. units conditions i s continuous source current mosfet symbol (body diode) CCC CCC showing the i sm pulsed source current integral reverse (body diode) ? CCC CCC p-n junction diode. v sd diode forward voltage CCC CCC 1.3 v t j = 25c, i s = 10a, v gs = 0v ? t rr reverse recovery time CCC 56 83 ns t j = 25c, i f = 10a q rr reverse recovery charge CCC 120 180 nc di/dt = 100a/s ?? t on forward turn-on time intrinsic turn-on time is negligible (turn-on is dominated by l s +l d ) source-drain ratings and characteristics a parameter min. typ. max. units conditions v (br)dss drain-to-source breakdown voltage 55 CCC CCC v v gs = 0v, i d = 250a ? v (br)dss / ? t j breakdown voltage temp. coefficient CCC 0.052 CCC v/c reference to 25c, i d =1ma ? r ds(on) static drain-to-source on-resistance CCC CCC 0.07 v gs =10v, i d = 10a ? v gs(th) gate threshold voltage 2.0 CCC 4.0 v v ds = v gs , i d = 250a g fs forward transconductance 4.5 CCC CCC s v ds = 25v, i d = 10a ? CCC CCC 25 a v ds = 55v, v gs = 0v CCC CCC 250 v ds = 44v, v gs = 0v, t j = 150c gate-to-source forward leakage CCC CCC 100 v gs = 20v gate-to-source reverse leakage CCC CCC -100 na v gs = -20v q g total gate charge CCC CCC 20 i d = 10a q gs gate-to-source charge CCC CCC 5.3 nc v ds = 44v q gd gate-to-drain ("miller") charge CCC CCC 7.6 v gs = 10v, see fig. 6 and 13 ?? t d(on) turn-on delay time CCC 4.9 CCC v dd = 28v t r rise time CCC 34 CCC i d = 10a t d(off) turn-off delay time CCC 19 CCC r g = 24 t f fall time CCC 27 CCC r d = 2.6 , see fig. 10 ?? between lead, CCC CCC and center of die contact c iss input capacitance CCC 370 CCC v gs = 0v c oss output capacitance CCC 140 CCC pf v ds = 25v c rss reverse transfer capacitance CCC 65 CCC ? = 1.0mhz, see fig. 5 ? electrical characteristics @ t j = 25c (unless otherwise specified) i gss ns i dss drain-to-source leakage current nh 7.5 l s internal source inductance 17 68 s d g downloaded from: http:///
irfz24ns/l fig 4. normalized on-resistance vs. temperature fig 2. typical output characteristics fig 1. typical output characteristics fig 3. typical transfer characteristics 1 10 100 0.1 1 10 100 i , d rain-to-source c urrent (a ) d v , drain-to-source voltage (v) ds vgs top 15v 10v 8.0v 7.0v 6.0v 5.5v 5.0v bott om 4.5v 20s pulse width t = 2 5c c a 4.5v 1 10 100 0.1 1 10 100 4.5v i , d rain-to-source c urrent (a ) d v , drain-to-source voltage (v) ds vgs top 15v 10v 8.0v 7.0v 6.0v 5.5v 5.0v bott om 4.5v 20s p ulse width t = 175c c a 1 10 100 4567891 0 t = 25c j gs v , gate-to-source voltage (v) d i , d rain -to-sou rce curren t (a) t = 175c j a v = 2 5 v 20s pulse w idth ds 0.0 0.5 1.0 1.5 2.0 2.5 3.0 -60 -40 -20 0 20 40 60 80 100 120 140 160 180 j t , junction temperature (c) r , drain -to -s ource o n re sistan ce ds(on) (norm alized) v = 10 v gs a i = 17 a d t j = 25c t j = 175c downloaded from: http:///
irfz24ns/l fig 6. typical gate charge vs. gate-to-source voltage fig 8. maximum safe operating area fig 5. typical capacitance vs. drain-to-source voltage fig 7. typical source-drain diode forward voltage 0 100 200 300 400 500 600 700 1 10 100 c, capacitance (pf) ds v , d rain-to-source voltage (v) a v = 0 v, f = 1m hz c = c + c , c shorte d c = c c = c + c gs iss gs gd ds rss gd oss ds gd c iss c oss c rs s 1 10 100 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.0 t = 25c j v = 0 v gs v , source-to-drain voltage (v) i , reverse drain cu rren t (a) sd sd a t = 175c j 1 10 100 1000 1 10 100 v , drain-to-source voltage (v) ds i , drain current (a ) ope ratio n in this a re a limite d by r d ds(on) 10s 100s 1ms 10ms a t = 25 c t = 17 5c single pulse cj 0 4 8 12 16 20 0 4 8 12 16 20 q , total gate charge (nc) g v , g ate-to -sou rce v oltage (v ) gs a for test circuit see fig ure 13 v = 4 4v v = 2 8v i = 1 0a dsds d downloaded from: http:///
irfz24ns/l fig 9. maximum drain current vs. case temperature fig 10a. switching time test circuit v ds 90%10% v gs t d(on) t r t d(off) t f fig 10b. switching time waveforms fig 11. maximum effective transient thermal impedance, junction-to-case v ds pulse width 1 s duty factor 0.1 % r d v gs r g d.u.t. 10v + - v dd 25 50 75 100 125 150 175 0 4 8 12 16 20 t , case temperature ( c) i , drain current (a) c d 0.01 0.1 1 10 0.00001 0.0001 0.001 0.01 0.1 1 notes: 1. duty factor d = t / t 2. peak t = p x z + t 1 2 j dm thjc c p t t dm 1 2 t , rectangular pulse duration (sec) thermal response (z ) 1 thjc 0.01 0.02 0.05 0.10 0.20 d = 0.50 single pulse (thermal response) downloaded from: http:///
irfz24ns/l fig 12a. unclamped inductive test circuit fig 12b. unclamped inductive waveforms fig 13a. basic gate charge waveform v ds l d.u.t. v dd i as t p 0.01 r g + - t p v ds i as v dd v (br)dss 10 v d.u.t. v ds i d i g 3ma v gs .3 f 50k .2 f 12v current regulator same type as d.u.t. current sampling resistors + - fig 13b. gate charge test circuit q g q gs q gd v g charge 10 v fig 12c. maximum avalanche energy vs. drain current 0 20 40 60 80 100 120 140 25 50 75 100 125 150 175 j e , s ingle pulse avalanche e nergy (m j) as a starting t , junction temperature (c) i to p 4.2 a 7 .2a bottom 10a v = 2 5v d dd downloaded from: http:///
irfz24ns/l peak diode recovery dv/dt test circuit p.w. period di/dt diode recovery dv/dt ripple 5% body diode forward drop re-appliedvoltage reverserecovery current body diode forward current v gs =10v v dd i sd driver gate drive d.u.t. i sd waveform d.u.t. v ds waveform inductor curent d = p. w . period + - + + + - - - fig 14. for n-channel hexfets * v gs = 5v for logic level devices ? ? ? r g v dd ? dv/dt controlled by r g ? driver same type as d.u.t. ? i sd controlled by duty factor "d" ? d.u.t. - device under test d.u.t circuit layout considerations ? low stray inductance ? ground plane ? low leakage inductance current transformer ? * downloaded from: http:///
irfz24ns/l d 2 pak package outline d 2 pak part marking information 10.16 (.400) r e f . 6.47 (.255) 6.18 (.243) 2.61 (.103) 2.32 (.091) 8.89 (.350) r e f. - b - 1.32 (.052) 1.22 (.048) 2.79 (.110) 2.29 (.090) 1.39 (.055) 1.14 (.045) 5.28 (.208) 4.78 (.188) 4.69 (.185) 4.20 (.165) 10.54 (.415) 10.29 (.405) - a - 2 1 3 15.49 (.610) 14.73 (.580) 3x 0.93 (.037) 0.69 (.027) 5.08 (.200) 3x 1.40 (.055) 1.14 (.045) 1.78 (.070) 1.27 (.050) 1.40 (.055) max. notes: 1 dimensions after solder dip. 2 dimensioning & tolerancing per ansi y14.5m, 1982. 3 controlling dimension : inch. 4 heatsink & lead dimensions do not include burrs. 0.55 (.022) 0.46 (.018) 0.25 (.010) m b a m minimum recommended footprint 11.43 (.450) 8.89 (.350) 17.78 (.700) 3.81 (.150) 2.08 (.082) 2x lead assignm ents 1 - g at e 2 - d r a in 3 - s ou rc e 2.54 (.100) 2x part number in ter nation al rectifier logo date code (yyww ) yy = year ww = week assembly lot code f530s 9b 1m 9246 a downloaded from: http:///
irfz24ns/l package outline to-262 outline to-262 part marking information downloaded from: http:///
irfz24ns/l tape & reel information d 2 pak world headquarters: 233 kansas st., el segundo, california 90245, tel: (310) 322 3331 european headquarters: hurst green, oxted, surrey rh8 9bb, uk tel: ++ 44 1883 732020 ir canada: 7321 victoria park ave., suite 201, markham, ontario l3r 2z8, tel: (905) 475 1897 ir germany: saalburgstrasse 157, 61350 bad homburg tel: ++ 49 6172 96590 ir italy: via liguria 49, 10071 borgaro, torino tel: ++ 39 11 451 0111 ir far east: k&h bldg., 2f, 30-4 nishi-ikebukuro 3-chome, toshima-ku, tokyo japan 171 tel: 81 3 3983 0086 ir southeast asia: 315 outram road, #10-02 tan boon liat building, singapore 0316 tel: 65 221 8371 http://www.irf.com/ data and specifications subject to change without notice. 9/97 3 4 4 trr feed direction 1.85 (.073) 1.65 (.065) 1.60 (.063) 1.50 (.059) 4.10 (.161) 3.90 (.153) trl feed direction 10.90 (.429) 10.70 (.421) 16.10 (.634) 15.90 (.626) 1.75 (.0 69 ) 1.25 (.0 49 ) 11 .6 0 (.45 7 ) 11 .4 0 (.44 9 ) 15 .4 2 (.60 9 ) 15 .2 2 (.60 1 ) 4.72 (.136) 4.52 (.178) 24.30 (.957) 23.90 (.941) 0.368 (.0145) 0.342 (.0135) 1.60 (.063) 1.50 (.059) 1 3.5 0 (.532 ) 1 2.8 0 (.504 ) 33 0.0 0 (14.17 3) m ax . 2 7.4 0 (1 .079 ) 2 3.9 0 (.9 41) 6 0.0 0 (2 .36 2) m in . 3 0.4 0 (1 .19 7) m a x . 26 .40 (1.03 9) 24.40 (.961) not es : 1. co mfo r ms to eia -418 . 2. co ntro llin g dim en sion : m illim eter . 3. dim ensio n m easured @ hub. 4. includes flange distortion @ outer edge. downloaded from: http:///
note: for the most current drawings please refer to the ir website at: http://www.irf.com/package/ downloaded from: http:///

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